With the advancement of performance and multifunctionality of consumer devices such as cellular phones, digital home appliances, network devices, and car navigation systems, the higher performance and functionality are demanded also for an embedded LSI serving as the center thereof. For its achievement, the performance improvement by the parallelization of processing units including application-specific accelerators has been proceeding.
On the other hand, LSIs to be embedded are under tight cost constraints and are required to operate under limited resources (resources such as power, computing units, memory bandwidth, and the number of pins).
One of effective ways to meet such contradictory demands is to optimally schedule processes to be executed in parallel and share the use of the limited resources among a plurality of processing units.
Conventionally, several technologies classified into a bus arbitration technology are known as those used when sharing resources among a plurality of units.
A method most generally used is a round-robin scheme, which is used in the technology disclosed in Japanese Patent Application Laid-Open Publication No. 2002-269032 (Patent Document 1).
Also, another method often used in a real-time compensation system is a TDMA (Time Division Multiple Access) scheme in which an exclusive resource right is fixedly provided in a time-division manner.
Furthermore, examples of a technology for sharing the power of the LSI among a plurality of tasks are disclosed in Japanese Patent Application Laid-Open Publication No. 2001-229040 (Patent Document 2) and Japanese Patent Application Laid-Open Publication No. 2002-202893 (Patent Document 3).
Also, Japanese Patent Application Laid-Open Publication No. 2003-298599 (Patent Document 4) describes the technology relating to the present invention.